diff --git a/src/sata.c b/src/sata.c index 3d9da8b..6917411 100644 --- a/src/sata.c +++ b/src/sata.c @@ -41,25 +41,21 @@ typedef struct tagFIS_PIO_SETUP { uint8_t bits; uint8_t status; // Status register uint8_t error; // Error register - // DWORD 1 uint8_t lba0; // LBA low register, 7:0 uint8_t lba1; // LBA mid register, 15:8 uint8_t lba2; // LBA high register, 23:16 uint8_t device; // Device register - // DWORD 2 uint8_t lba3; // LBA register, 31:24 uint8_t lba4; // LBA register, 39:32 uint8_t lba5; // LBA register, 47:40 uint8_t rsv2; // Reserved - // DWORD 3 uint8_t countl; // Count register, 7:0 uint8_t counth; // Count register, 15:8 uint8_t rsv3; // Reserved uint8_t e_status; // New value of status register - // DWORD 4 uint16_t tc; // Transfer count uint8_t rsv4[2]; // Reserved @@ -70,7 +66,6 @@ typedef struct tagFIS_DATA { uint8_t fis_type; // FIS_TYPE_DATA uint8_t bits; uint8_t rsv1[2]; // Reserved - // DWORD 1 ~ N uint32_t data[1]; // Payload } FIS_DATA; @@ -81,24 +76,20 @@ typedef struct tagFIS_REG_D2H { uint8_t bits; uint8_t status; // Status register uint8_t error; // Error register - // DWORD 1 uint8_t lba0; // LBA low register, 7:0 uint8_t lba1; // LBA mid register, 15:8 uint8_t lba2; // LBA high register, 23:16 uint8_t device; // Device register - // DWORD 2 uint8_t lba3; // LBA register, 31:24 uint8_t lba4; // LBA register, 39:32 uint8_t lba5; // LBA register, 47:40 uint8_t rsv2; // Reserved - // DWORD 3 uint8_t countl; // Count register, 7:0 uint8_t counth; // Count register, 15:8 uint8_t rsv3[2]; // Reserved - // DWORD 4 uint8_t rsv4[4]; // Reserved } FIS_REG_D2H; @@ -109,25 +100,21 @@ typedef struct tagFIS_REG_H2D { uint8_t bits; uint8_t command; // Command register uint8_t featurel; // Feature register, 7:0 - // DWORD 1 uint8_t lba0; // LBA low register, 7:0 uint8_t lba1; // LBA mid register, 15:8 uint8_t lba2; // LBA high register, 23:16 uint8_t device; // Device register - // DWORD 2 uint8_t lba3; // LBA register, 31:24 uint8_t lba4; // LBA register, 39:32 uint8_t lba5; // LBA register, 47:40 uint8_t featureh; // Feature register, 15:8 - // DWORD 3 uint8_t countl; // Count register, 7:0 uint8_t counth; // Count register, 15:8 uint8_t icc; // Isochronous command completion uint8_t control; // Control register - // DWORD 4 uint8_t reserved0[4]; } FIS_REG_H2D; @@ -137,21 +124,15 @@ typedef struct tagFIS_DMA_SETUP { uint8_t fis_type; // FIS_TYPE_DMA_SETUP uint8_t bits; uint8_t rsved[2]; // Reserved - //DWORD 1&2 - uint64_t DMAbufferID; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. // SATA Spec says host specific and not in Spec. Trying AHCI spec might work. - - //DWORD 3 + //DWORD 3 uint32_t rsvd; //More reserved - //DWORD 4 uint32_t DMAbufOffset; //Byte offset into buffer. First 2 bits must be 0 - //DWORD 5 uint32_t TransferCount; //Number of bytes to transfer. Bit 0 must be 0 - //DWORD 6 uint32_t resvd; //Reserved } FIS_DMA_SETUP; @@ -167,50 +148,42 @@ typedef struct FIS_DEV_BITS { typedef volatile struct tagHBA_FIS { // 0x00 - FIS_DMA_SETUP dsfis; // DMA Setup FIS - uint8_t pad0[4]; - + FIS_DMA_SETUP dsfis; // DMA Setup FIS + uint8_t pad0[4]; // 0x20 - FIS_PIO_SETUP psfis; // PIO Setup FIS - uint8_t pad1[12]; - + FIS_PIO_SETUP psfis; // PIO Setup FIS + uint8_t pad1[12]; // 0x40 - FIS_REG_D2H rfis; // Register – Device to Host FIS - uint8_t pad2[4]; - + FIS_REG_D2H rfis; // Register – Device to Host FIS + uint8_t pad2[4]; // 0x58 - FIS_DEV_BITS sdbfis; // Set Device Bit FIS - + FIS_DEV_BITS sdbfis; // Set Device Bit FIS // 0x60 - uint8_t ufis[64]; - + uint8_t ufis[64]; // 0xA0 - uint8_t rsv[0x100-0xA0]; + uint8_t rsv[0x100-0xA0]; } HBA_FIS; #define PRDT_BITS_DBC_MASK 0x003FFFFF #define PRDT_BITS_INTERRUPT 0x80000000 typedef struct tagHBA_PRDT_ENTRY { - uint32_t dba; // Data base address - uint32_t dbau; // Data base address upper 32 bits - uint32_t rsv0; // Reserved + uint32_t dba; // Data base address + uint32_t dbau; // Data base address upper 32 bits + uint32_t rsv0; // Reserved uint32_t bits; } HBA_PRDT_ENTRY; typedef struct tagHBA_CMD_TBL { // 0x00 - uint8_t cfis[64]; // Command FIS - + uint8_t cfis[64]; // Command FIS // 0x40 - uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes - + uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes // 0x50 - uint8_t rsv[48]; // Reserved - + uint8_t rsv[48]; // Reserved // 0x80 // FIXME turn this into a Flexible Array Member - HBA_PRDT_ENTRY prdt_entry[8]; // Physical region descriptor table entries, 0 ~ 65535 + HBA_PRDT_ENTRY prdt_entry[8]; // Physical region descriptor table entries, 0 ~ 65535 } HBA_CMD_TBL; #define CHDR_BITS_CFL_MASK 0x001F @@ -227,17 +200,14 @@ typedef struct tagHBA_CMD_HEADER { // DW0 uint16_t bits; uint16_t prdtl; // Physical region descriptor table length in entries - // DW1 volatile uint32_t prdbc; // Physical region descriptor byte count transferred - // DW2, 3 uint32_t ctba; // Command table descriptor base address uint32_t ctbau; // Command table descriptor base address upper 32 bits - // DW4 - 7 uint32_t reserved1[4]; // Reserved -} HBA_CMD_HEADER; // HBA Port for individual devices +} HBA_CMD_HEADER; // HBA Port for individual devices typedef struct __attribute__((packed)) HBA_PORT { uint32_t clb; // Command List Base