Initializing host state
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fb720ed106
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f374da687b
4 changed files with 104 additions and 24 deletions
20
include/x86/gdt.h
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include/x86/gdt.h
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#ifndef _VISOR_GDT_H_
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#define _VISOR_GDT_H_
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#include <stdint.h>
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__attribute__ ((packed))
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struct GDTR {
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uint16_t limit;
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uint64_t base;
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};
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static inline struct GDTR
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storegdt(void)
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{
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struct GDTR gdtr;
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__asm__ ("sgdt %0\n\t" : "=m"(gdtr));
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return gdtr;
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}
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#endif
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20
include/x86/idt.h
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include/x86/idt.h
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#ifndef _VISOR_IDT_H_
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#define _VISOR_IDT_H_
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#include <stdint.h>
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__attribute__ ((packed))
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struct IDTR {
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uint16_t limit;
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uint64_t base;
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};
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static inline struct IDTR
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storeidt(void)
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{
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struct IDTR idtr;
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__asm__ ("sidt %0\n\t" : "=m"(idtr));
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return idtr;
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}
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#endif
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@ -19,9 +19,10 @@
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#define IA32_VMX_CR4_FIXED1 0x489
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#define IA32_VMX_CR4_FIXED1 0x489
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#define IA32_VMX_VMCS_ENUM 0x48A
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#define IA32_VMX_VMCS_ENUM 0x48A
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#define IA32_EFER 0xC0000080
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#define IA32_EFER 0xC0000080
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#define IA32_FS_BASE 0xC0000100
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#define IA32_FS_BASE 0xC0000100
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#define IA32_GS_BASE 0xC0000101
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#define IA32_GS_BASE 0xC0000101
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#define IA32_KERNEL_GS_BASE 0xC0000102
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static inline uint32_t
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static inline uint32_t
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readmsr32(uint32_t msr)
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readmsr32(uint32_t msr)
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81
src/vintel.c
81
src/vintel.c
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@ -5,6 +5,8 @@
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#include <cpuid.h>
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#include <cpuid.h>
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#include <x86/msr.h>
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#include <x86/msr.h>
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#include <x86/cr.h>
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#include <x86/cr.h>
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#include <x86/idt.h>
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#include <x86/gdt.h>
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#include <x86/vmx.h>
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#include <x86/vmx.h>
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#include "virt.h"
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#include "virt.h"
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@ -97,25 +99,61 @@ vintel_init_guest(void)
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vmwrite(GUEST_SYSENTER_EIP, readmsr64(0x176));
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vmwrite(GUEST_SYSENTER_EIP, readmsr64(0x176));
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}
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}
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#if 0
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#define HOST_ES_SELECTOR 0xC00
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#define HOST_CS_SELECTOR 0xC02
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#define HOST_SS_SELECTOR 0xC04
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#define HOST_DS_SELECTOR 0xC06
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#define HOST_FS_SELECTOR 0xC08
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#define HOST_GS_SELECTOR 0xC0A
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#define HOST_TR_SELECTOR 0xC0C
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#define HOST_CR0 0x6C00
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#define HOST_CR3 0x6C02
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#define HOST_CR4 0x6C04
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#define HOST_RSP 0x6C14
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#define HOST_RIP 0x6C16
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#define HOST_IA32_PAT 0x2C00
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#define HOST_IA32_EFER 0x2C02
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#define HOST_FS_BASE 0x6C06
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#define HOST_GS_BASE 0x6C08
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#define HOST_TR_BASE 0x6C0A
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#define HOST_SYSENTER_CS 0x4C00
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#define HOST_SYSENTER_ESP 0x6C10
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#define HOST_SYSENTER_EIP 0x6C12
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#define HOST_GDTR_BASE 0x6C0C
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#define HOST_IDTR_BASE 0x6C0E
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#if 1
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static void
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static void
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vintel_init_host(void)
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vintel_init_host(void)
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{
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{
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#if 0
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// Read TR
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// Read TR
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trBase.LowPart = ((trItem[0] >> 16) & 0xFFFF) | ((trItem[1] & 0xFF) << 16) | ((trItem[1] & 0xFF000000) >> 8);
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trBase.LowPart = ((trItem[0] >> 16) & 0xFFFF) | ((trItem[1] & 0xFF) << 16) | ((trItem[1] & 0xFF000000) >> 8);
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trBase.HighPart = trItem[2];
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trBase.HighPart = trItem[2];
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#endif
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uint64_t trBase = 0x0;
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uint64_t trSelector = 0x0;
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uint64_t hostSP = 0x0;
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uint64_t hostIP = 0x0;
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// Set TR
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// Set TR
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vmwrite(HOST_TR_BASE, trBase.QuadPart);
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vmwrite(HOST_TR_BASE, trBase);
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vmwrite(HOST_TR_SELECTOR, trSelector);
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vmwrite(HOST_TR_SELECTOR, trSelector);
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// Set segment selectors
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// Set segment selectors
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vmwrite(HOST_ES_SELECTOR, AsmReadES() & 0xfff8);
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vmwrite(HOST_ES_SELECTOR, reades() & 0xfff8);
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vmwrite(HOST_CS_SELECTOR, AsmReadCS() & 0xfff8);
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vmwrite(HOST_CS_SELECTOR, readcs() & 0xfff8);
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vmwrite(HOST_SS_SELECTOR, AsmReadSS() & 0xfff8);
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vmwrite(HOST_SS_SELECTOR, readss() & 0xfff8);
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vmwrite(HOST_DS_SELECTOR, AsmReadDS() & 0xfff8);
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vmwrite(HOST_DS_SELECTOR, readds() & 0xfff8);
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vmwrite(HOST_FS_SELECTOR, AsmReadFS() & 0xfff8);
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vmwrite(HOST_FS_SELECTOR, readfs() & 0xfff8);
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vmwrite(HOST_GS_SELECTOR, AsmReadGS() & 0xfff8);
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vmwrite(HOST_GS_SELECTOR, readgs() & 0xfff8);
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// Set control registers
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// Set control registers
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vmwrite(HOST_CR0, readcr0());
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vmwrite(HOST_CR0, readcr0());
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@ -123,23 +161,23 @@ vintel_init_host(void)
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vmwrite(HOST_CR4, readcr4());
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vmwrite(HOST_CR4, readcr4());
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// Set RSP and RIP
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// Set RSP and RIP
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vmwrite(HOST_RSP, (ULONG64)pVcpu->VmxHostStackBase);
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vmwrite(HOST_RSP, hostSP);
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vmwrite(HOST_RIP, HostEip);
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vmwrite(HOST_RIP, hostIP);
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// Set MSRs
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// Set MSRs
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vmwrite(HOST_IA32_PAT, __readmsr(IA32_MSR_PAT));
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vmwrite(HOST_IA32_PAT, readmsr64(IA32_PAT));
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vmwrite(HOST_IA32_EFER, __readmsr(IA32_MSR_EFER));
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vmwrite(HOST_IA32_EFER, readmsr64(IA32_EFER));
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vmwrite(HOST_FS_BASE, __readmsr(IA32_FS_BASE));
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vmwrite(HOST_FS_BASE, readmsr64(IA32_FS_BASE));
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vmwrite(HOST_GS_BASE, __readmsr(IA32_GS_KERNEL_BASE));
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vmwrite(HOST_GS_BASE, readmsr64(IA32_KERNEL_GS_BASE));
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vmwrite(HOST_IA32_SYSENTER_CS, __readmsr(0x174));
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vmwrite(HOST_SYSENTER_CS, readmsr64(0x174));
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vmwrite(HOST_IA32_SYSENTER_ESP, __readmsr(0x175));
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vmwrite(HOST_SYSENTER_ESP, readmsr64(0x175));
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vmwrite(HOST_IA32_SYSENTER_EIP, __readmsr(0x176));
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vmwrite(HOST_SYSENTER_EIP, readmsr64(0x176));
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// Set GDT and IDT
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// Set GDT and IDT
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GdtTable idtTable;
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struct GDTR gdtr = storegdt();
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__sidt(&idtTable);
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struct IDTR idtr = storeidt();
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vmwrite(HOST_GDTR_BASE, gdtTable.Base);
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vmwrite(HOST_GDTR_BASE, gdtr.base);
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vmwrite(HOST_IDTR_BASE, idtTable.Base);
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vmwrite(HOST_IDTR_BASE, idtr.base);
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}
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}
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#endif
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#endif
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@ -186,6 +224,7 @@ vintel_enable(void)
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Print(L"VMPTRLD Status: %p\n", (void *)status);
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Print(L"VMPTRLD Status: %p\n", (void *)status);
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vintel_init_guest();
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vintel_init_guest();
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vintel_init_host();
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}
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}
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struct virt_vtable virt_vtable_intel = {
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struct virt_vtable virt_vtable_intel = {
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